Методи та засоби апаратної реалізації та вибору алгоритмів заміщення даних у кеш-пам'яті мікропроцесорів

Abstract

Dissertation for the degree candidate of technical sciences in specialty of 05.13.05 – Computer systems and components (12 - Information technologies). – National Aerospace University named after M.E. Zhukovsky "Kharkіv Aviation Institute", National Technical University "Kharkiv Polytechnic Institute", Ministry of Education and Science of Ukraine, Kharkiv, 2021. The dissertation work is devoted to the development of methods and means of hardware implementation and the select of algorithms for substitution data in the cache-memory of microprocessors. Scientific results are: 1) the automaton model and the means of implementing the PLRU algorithm of substitution data in the processor cache by changing the types and simplifying the combination logic of managing the update of memory elements which provides increased high-speed performance and reduced complexity of these tools have been further developed; 2) for the first time proposed method and means of implementing adaptive algorithms for substitution data in the processor cache, which, unlike the known ones, are based on the construction and analysis of compatibility matrices of algorithms and allow you to select a substitution algorithm depending on the results of dynamic prediction of program branches, which provides increased high-speed performance of processor; 3) improved means of monitoring implementation of data substitution algorithms in the processor memory cache by using a unified automaton model that takes into account the number of data selection directions of substitution, as well as estimates of the complexity of the basic components of the monitoring means, which allows estimating the increase in reliability per unit of hardware costs; 4) improved method of selecting algorithms and implementation means for substitution data in the processor cache by including in a multitude of algorithms with control and adaptation, ordering of them according to high-speed performance, complexity and reliability indicators, which allows improving corresponding processor indicators; the proposed methods and tools are allow to improve high-speed performance and reliability, as well as reduce the complexity of the hardware costs of the data substitution modules of the associative memory cache and the associative translation look-a-side buffer, which allow to increase the high-speed performance, energy efficiency and reliability of the processor as a whole.