Перегляд за Автор "Salnikov, Dmytro"
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Документ Acceleration of boolean gene regulatory networks analysis using FPGA(Національний технічний університет "Харківський політехнічний інститут", 2023) Vasylchenkov, Oleg; Salnikov, Dmytro; Karaman, DmytroGene expression does not occur arbitrarily and spontaneously, it obeys certain patterns that can be expressed as a connected graph or network. The disclosure of these patterns requires a large amount of experimental research and accumulation of necessary statistical information. Then this information is subjected to mathematical processing, which involves significant computing resources and takes a lot of time. Boolean networks are often used as the basis for building mathematical models in those calculations. Recently, models based on Boolean networks have increasingly grown in size and complexity causing increased demands on traditional software solutions and computing tools. Field-programmable gate arrays (FPGAs) are a powerful and reconfigurable platform for implementing efficient and high-performance computing. The use of FPGA will significantly speed up the process of calculating sequential chains of gene states, both through the use of hardware acceleration in the calculation of logical dependencies, and through the implementation of an array of parallel computing cores, each of which can perform its own individual task. Another solution that can significantly simplify the work of researchers of gene regulation networks is the creation of a universal computing architecture that will allow dynamic reconfiguration of its internal structure when the task or logical dependencies for the current Boolean network change. Such a solution will relieve the researcher of the need to perform the entire set of actions for the technological preparation of a new FPGA configuration, from making changes to the HDL code that describes the network to uploading the updated configuration to the hardware accelerator. The article discusses how to use FPGA for the implementation and modeling of arbitrary Boolean networks, describes the concept of a universal reconfigurable architecture of a logical dependency calculating core for an arbitrary Boolean network and proposes a practical implementation of such a calculating core for modeling gene regulation networks.Документ Conveyorized implementation of aswm image filter on PLD(PC Technology Center, 2021) Vasylchenkov, Oleg; Liberg, Igor; Mozhaiev, Mykhailo; Salnikov, DmytroThe object of research is the adaptive switching weighted median image filter (ASWM) algorithm. This algorithm is one of the most effective in the field of impulse noise suppression. The computational complexity and algorithmic features of this adaptive nonlinear filter make it impossible to implement a filter that works in real time on modern PLD microcircuits. The most problematic areas of the algorithm are the weight coefficient estimation cycle, which has no limit on the number of iterations and contains a large number of division operations. This does not allow implementing the filter on PLDs with a sufficiently effective method. In the course of the research, the programming model of the filter in Python was used. The performance of the algorithm was assessed using the Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) metrics.Modeling made it possible to find out empirically the number of iterations of the cycle for estimating the weight coefficients at different levels of noise density and to estimate the effect of artificial limitation of the maximum number of iterations on the filter performance. Regardless of the intensity of the noise impact, the algorithm performs less than 40 iterations of the evaluation cycle. Let’s also simulate the operation of the algorithm with different variants of the division module implementation. The paper considers the main of them and offers the most optimal in terms of the ratio of accuracy/hardware costs for implementation. Thus, a modified algorithm was proposed that does not have these disadvantages.Thanks to modifications of the algorithm, it is possible to implement a pipelined ASWM image filter on modern PLDs. The filter is synthesized for the main families of Intel PLDs. The implementation, which is not inferior in terms of SSIM and PSNR metrics to the original algorithm, requires less than 65,000 FPGA logical cells and allows filtering of monochrome images with FullHD resolution at 48 frames/s at a clock frequency of 100 MHz.Документ Fixed-point Realisation of Fast Nonlinear Fourier Transform Algorithm for FPGA Implementation of Optical Data Processing(SPIE, 2021) Vasylchenkova, Anastasiia; Salnikov, Dmytro; Karaman, Dmytro; Vasylchenkov, Oleg; Prilepskiy, JaroslawThe nonlinear Fourier transform (NFT) based signal processing has attracted considerable attention as a promising tool for fibre nonlinearity mitigation in optical transmission. However, the mathematical complexity of NFT algorithms and the noticeable distinction of the latter from the “conventional” (Fourier-based) methods make it difficult to adapt this approach for practical applications. In our work, we demonstrate a hardware implementation of the fast direct NFT operation: it is used to map the optical signal onto its nonlinear Fourier spectrum, i.e. to demodulate the data. The main component of the algorithm is the matrix-multiplier unit, implemented on field-programmable gate arrays (FPGA) and used in our study for the estimation of required hardware resources. To design the best performing implementation in limited resources, we carry out the processing accuracy analysis to estimate the optimal bit width. The fast NFT algorithm that we analyse, is based on the FFT, which leads to the O(N log22 N) method’s complexity for the signal consisting of N samples. Our analysis revealed the significant demand in DSP blocks on the used board, which is caused by the complex-valued matrix operations and FFTs. Nevertheless, it seems to be possible to utilise further the parallelisation of our NFT-processing implementation for the more efficient NFT hardware realisation.Документ Highly reconfigurable soft-CPU based peripheral modules design(Національний технічний університет "Харківський політехнічний інститут", 2023) Salnikov, Dmytro; Karaman, Dmytro; Krylova, ViktoriiaWhen developing microcontrollers, manufacturers try to include as many different types of peripherals as possible in order to increase the marketing attractiveness of their products. On the one hand, with a large assortment of various peripheral modules, it is very difficult to implement several devices of the same type in the microcontroller: manufacturers are mainly limited to 1-2 instances, in rare cases 4 modules of the same type are included. On the other hand, most software projects do not use all the peripherals of modern microcontrollers and many devices are left unused, while there may be a shortage of other types of modules. Another problem that has become especially noticeable for microcontrollers used in the field of IoT is the cryptographic protection of data that is transmitted through built-in information exchange interfaces. The main efforts of researchers and developers of cryptographic data protection methods were aimed at reducing energy-intensive operations, memory access iterations and speeding up encryption processes while maintaining a high level of cryptographic protection and enabling efficient data distribution within IoT devices networks. Research results. This paper presents an alternative approach to the manufacture of peripheral modules as part of microcontrollers. The authors propose to use a configurable software processor module based on the MIPS architecture with a reduced instruction set and limited capabilities. Conclusions. This approach would make it possible to dynamically change the functionality of peripheral modules in accordance with the requirements of the developed software solution, which in turn will increase the efficiency of the microcontroller chips capabilities utilization. In addition, the transfer of data stream encryption functions to the reconfigurable core of the peripheral module will provide fast and transparent cryptographic protection, as well as allow offloading the microcontroller core and increasing the energy efficiency of chips while reducing their production cost.Документ Searching for Optimal Control Parameters of Thermal Object Using Pulse-Width Modulation (PWM) Control with Predictive Filter(Lviv Polytechnic Publishing House, 2015) Yevseienko, Oleg; Gapon, Anatoliy; Salnikov, DmytroThe thesis is devote to the temperature control of objects with lumped or distributed parameters. The problems of choosing the right value of regulator’s heater power and prediction period are discussed. The major attention is paid to the process of searching the minimum value of control quantities. It is shown that the approximated second-order plane has an exact accordance with the original data. It is concluded that algorithm of PWM-control with prediction filter provides good quality control.