Кафедра "Автоматика та управління в технічних системах"

Постійне посилання колекціїhttps://repository.kpi.kharkov.ua/handle/KhPI-Press/5193

Офіційний сайт кафедри http://web.kpi.kharkov.ua/auts

Кафедра "Автоматика та управління в технічних системах" виділилася в самостійну одиницю у складі електромеханічного факультету Харківського електротехнічного інституту в 1948 році з кафедри "Електричні апарати". У момент створення вона мала назву Кафедра "Автоматика і телемеханіка". Першим завідувачем кафедри став кандидат технічних наук, доцент Файвель Аронович Ступель.

За роки свого існування кафедра випустила понад 3500 фахівців.

Кафедра входить до складу Навчально-наукового інституту комп'ютерного моделювання, прикладної фізики та математики Національного технічного університету "Харківський політехнічний інститут".

У складі науково-педагогічного колективу кафедри працюють 1 доктор технічних наук, 9 кандидатів технічних наук; 1 співробітник має звання професора, 7 – звання доцента.

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20212

Налаштування

ORCID: search.filters.orcid.https://orcid.org/ 0000-0002-0490-4061

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  • Ескіз
    Документ
    Fixed-point Realisation of Fast Nonlinear Fourier Transform Algorithm for FPGA Implementation of Optical Data Processing
    (SPIE, 2021) Vasylchenkova, Anastasiia; Salnikov, Dmytro; Karaman, Dmytro; Vasylchenkov, Oleg; Prilepskiy, Jaroslaw
    The nonlinear Fourier transform (NFT) based signal processing has attracted considerable attention as a promising tool for fibre nonlinearity mitigation in optical transmission. However, the mathematical complexity of NFT algorithms and the noticeable distinction of the latter from the “conventional” (Fourier-based) methods make it difficult to adapt this approach for practical applications. In our work, we demonstrate a hardware implementation of the fast direct NFT operation: it is used to map the optical signal onto its nonlinear Fourier spectrum, i.e. to demodulate the data. The main component of the algorithm is the matrix-multiplier unit, implemented on field-programmable gate arrays (FPGA) and used in our study for the estimation of required hardware resources. To design the best performing implementation in limited resources, we carry out the processing accuracy analysis to estimate the optimal bit width. The fast NFT algorithm that we analyse, is based on the FFT, which leads to the O(N log22 N) method’s complexity for the signal consisting of N samples. Our analysis revealed the significant demand in DSP blocks on the used board, which is caused by the complex-valued matrix operations and FFTs. Nevertheless, it seems to be possible to utilise further the parallelisation of our NFT-processing implementation for the more efficient NFT hardware realisation.
  • Ескіз
    Документ
    Conveyorized implementation of aswm image filter on PLD
    (PC Technology Center, 2021) Vasylchenkov, Oleg; Liberg, Igor; Mozhaiev, Mykhailo; Salnikov, Dmytro
    The object of research is the adaptive switching weighted median image filter (ASWM) algorithm. This algorithm is one of the most effective in the field of impulse noise suppression. The computational complexity and algorithmic features of this adaptive nonlinear filter make it impossible to implement a filter that works in real time on modern PLD microcircuits. The most problematic areas of the algorithm are the weight coefficient estimation cycle, which has no limit on the number of iterations and contains a large number of division operations. This does not allow implementing the filter on PLDs with a sufficiently effective method. In the course of the research, the programming model of the filter in Python was used. The performance of the algorithm was assessed using the Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) metrics.Modeling made it possible to find out empirically the number of iterations of the cycle for estimating the weight coefficients at different levels of noise density and to estimate the effect of artificial limitation of the maximum number of iterations on the filter performance. Regardless of the intensity of the noise impact, the algorithm performs less than 40 iterations of the evaluation cycle. Let’s also simulate the operation of the algorithm with different variants of the division module implementation. The paper considers the main of them and offers the most optimal in terms of the ratio of accuracy/hardware costs for implementation. Thus, a modified algorithm was proposed that does not have these disadvantages.Thanks to modifications of the algorithm, it is possible to implement a pipelined ASWM image filter on modern PLDs. The filter is synthesized for the main families of Intel PLDs. The implementation, which is not inferior in terms of SSIM and PSNR metrics to the original algorithm, requires less than 65,000 FPGA logical cells and allows filtering of monochrome images with FullHD resolution at 48 frames/s at a clock frequency of 100 MHz.